The IDT91305 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at speeds from 10 to 133 MHz.
IDT91305 is a zero delay buffer that provides synchronization between the input and output. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than +/- 350 pS, the part acts as a zero delay buffer.
The IDT91305 comes in an eight pin 150 mil SOIC package. It has five output clocks. In the absence of REF input, will be in the power down mode. In this mode, the PLL is turned off and the output buffers are pulled low. Power down mode provides the lowest power consumption for a standby condition.
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.
Pkg. Type |
Lead Count (#) |
Temp. Grade |
Pb (Lead) Free |
Carrier Type |
Buy / Sample |
|
---|---|---|---|---|---|---|
Part Number | ||||||
TSSOP | 8 | I | Yes | Tube | ||
TSSOP | 8 | I | Yes | Reel | ||
TSSOP | 8 | C | Yes | Tube | ||
TSSOP | 8 | C | Yes | Reel | ||
SOIC | 8 | I | Yes | Tube | ||
SOIC | 8 | I | Yes | Reel | ||
SOIC | 8 | C | Yes | Tube | ||
SOIC | 8 | C | Yes | Reel |