Overview

The 621 is a low skew, single input to four output, clock buffer. The device operates from a single 1.2 to 1.8 volt supply and has a 3.3 volt tolerant input, making it ideal for level translation. IDT makes many non-PLL and PLL based low skew output devices as well as Zero Delay Buffers to synchronize clocks. Contact us for all of your clocking needs.

621 - Block Diagram
621 - Pinout
621 - Block Diagram
621 - Pinout
  • Low skew outputs (150 ps)
  • Packaged in 8-pin SOIC or 8-pin DFN (2x2mm)
  • RoHS 5 or RoHS 6 (lead-free) package
  • Low power CMOS technology
  • Operating voltages of 1.2 V to 1.8 V
  • Output Enable pin tri-states outputs
  • 3.3 V tolerant input clock
  • Industrial or commercial temperature ranges

Documentation

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

Explore ECAD Models
Diagram of ECAD Models

Product Options

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Buy / Sample
    Part Number
    621MILF
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    		SOIC 8 I Yes Tube
    621MILFT
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    view_in_ar
    		SOIC 8 I Yes Reel
    621MLF
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    memory
    view_in_ar
    		SOIC 8 C Yes Tube
    621MLFT
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    memory
    view_in_ar
    		SOIC 8 C Yes Reel
    621NILFT
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    view_in_ar
    		VFQFPN 8 I Yes Reel
    621NLFT
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    view_in_ar
    		VFQFPN 8 C Yes Reel
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