Overview

9FG1200-1 follows the Intel DB1200GS Differential Buffer Specification. This buffer provides 12 output clocks for CPU Host Bus, PCIe Gen2, or Fully Buffered DIMM applications. The outputs are configured with two groups. Both groups (DIF 9:0) and (DIF 11:10) can be equal to or have a gear ratio to the input clock. A differential CPU clock from a CK410B+ main clock generator, such as the 932S421, drives the . The can provide outputs up to 400MHz.

9FG1200D-1 - Block Diagram
9FG1200D-1 - Pinout
9FG1200D-1 - Block Diagram
9FG1200D-1 - Pinout
  • Drives 2 channels of 4 FBDIMMs (total of 8 FBDIMMs)
  • Power up default is all outputs in 1:1 mode
  • DIF_(9:0) can be "gear-shifted" from the input CPU Host Clock
  • DIF_(11:10) can be "gear-shifted" from the input CPU Host Clock
  • Spread spectrum compatible
  • Supports output clock frequencies up to 400 MHz
  • 8 Selectable SMBus addresses
  • SMBus address determines PLL or Bypass mode
  • DIF output cycle-to-cycle jitter < 50ps
  • DIF output-to-output skew < 100ps across all outputs in 1:1 mode
  • 56-pin SSOP/TSSOP package
  • RoHS compliant packaging

Documentation

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

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Diagram of ECAD Models

Product Options

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Buy / Sample
    Part Number
    9FG1200DG-1LF
    circleObsolete
    memory
    view_in_ar
    		TSSOP 56 C Yes Tube
    9FG1200DG-1LFT
    circleObsolete
    memory
    view_in_ar
    		TSSOP 56 C Yes Reel
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